1. Field of the Invention
The present invention relates to a method of forming self-aligned unlanded via holes of integrated circuits, and more particularly to a process of forming self-aligned unlanded via holes by depositing an HDP-CVD dielectric layer and a silicon nitride layer within.
2. Description of the Prior Art
The current trend in VLSI design toward denser and more complex circuitry produces closely spaced and smaller geometries on larger wafers, which results in narrower and longer interconnect lines. The increase of circuit density has obviously improved the performance of electric devices by reducing RC delay time and effectively decreased the cost. However, one of the limitations in a VLSI process is the size of a via hole (or via plug) which is formed for connecting two conductive layers. How to exactly define a smaller via hole to a proper position is a challenging issue for a VLSI fabrication.
The size of a via hole is usually smaller than the metal line width for avoiding the problem of misalignment induced during a step of photolithography. Please referring to FIG. 1, a cross-sectional view of part of a partially fabricated integrated circuit structure with via plugs according to the prior art is illustrated, the misalignment of via holes could induce a problem of over-etch to damage the first dielectric layer 100a and even the devices beneath. As a result, the misaligned via plugs 60b will be a problem of electric short.
Therefore, a self-aligned contact (SAC) process of forming via holes is developed for decreasing the size of each via hole with the misalignment problem.